I/O interfacing circuits –Hand shaking,serial and parallel interfacing – Address decoding Interfacing chips Programmable peripheral interfacing. In this presentation we get to know about keyboard Features, Cpu interface pins, Key board Data, Display data, Timing and control. Intel Programmable Key Board/Display Interface is available in the The description of pins of Programmable keyboard/display interface is given.

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Strobed keyboard, encoded display scan. The Keyboard can be interfaced either in the interrupt or the polled mode. Return lines are inputs used to sense key depression in the keyboard matrix. This unit controls the flow of data through the microprocessor. The address inputs select one of the four internal registers with the as follows: Used internally for timing. This mode deals with display-related operations.

The Shift input line status is stored along with every key code in FIFO in the scanned keyboard mode. In the Interrupt modethe processor is requested service only if any key is pressed, otherwise the CPU will continue with its main task.

These lines can be programmed as encoded or decoded, using the mode control register. Clears the IRQ signal to the microprocessor.

In the encoded mode, the counter provides the binary count that is to be externally decoded to provide the scan lines for the keyboard and display. Shift connects to Shift key on keyboard. Output that blanks the displays. Causes DRAM memory system to be refreshed.


DD Function Encoded keyboard with 2-key lockout Decoded keyboard with 2-key lockout Encoded keyboard with N-key rollover Decoded keyboard with N-key rollover Encoded sensor matrix Decoded sensor matrix Strobed keyboard, encoded display scan Strobed keyboard, decoded display scan Encoded: In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is loaded with the status keyhoard their corresponding row of sensors into the matrix.

Pinout Definition A0: Clears the display or FIFO. This unit first scans the key closure row-wise, if found then the keyboard debounce unit debounces the key entry.

This unit contains registers to store the keyboard, display modes, and other operations as programmed by the CPU. It is enabled only when D is low. SL outputs are active-low only one low at any time. It has two modes i. Pins SL2-SL0 sequentially scan each column through a counting operation. Interface of 2 Keyboard type is programmed next. It interfqce an internal pull up.

Intel – Wikipedia

Controls up to a digit numerical display. Till it is pulled low with a key closure, it is pulled up internally to keep it high.

DD field selects either: The unterface is pulled down with a key closure. Decoded keyboard with N-key rollover. Keyboard has a built-in FIFO 8 character buffer.

Intel 8279

The scans RL pins synchronously with the scan. There are 6 modes of operation for each counter: These lines are set to 0 when any key is pressed. Encoded keyboard with N-key rollover. The display is controlled from an internal 16×8 RAM that stores the coded display information. Chip select that enables programming, reading the keyboard, etc. If more than 8 characters are entered in the FIFO, then it means more than eight keys are pressed at a time.


The timing and control unit handles the timings for the operation of the circuit. Minimum count is 1 all modes except 2 and 3 with minimum count of 2.

8279 – Programmable Keyboard

The previous example illustrates an encoded keyboard, external decoder used to drive matrix. Sl outputs are active-high, follow binary dispkay pattern or Consists of bidirectional pins that connect to data bus on micro. These are the scan lines used to scan the keyboard matrix and display the digits. Programs internal clk, sets scan and debounce times.

Used for controlling real-time events such as real-time clock, events counter, and motor speed and direction control. The 74LS drives 0’s on one line at a time.

8729 the Polled modethe CPU periodically reads an internal flag of to check whether any key is pressed or not with key pressure.