DS90LVTMTC: DS90LV – V or 5V LVDS Driver/Receiver, Package: Soic Narrow, Pin Nb= DS 90 LV TMTC · DS90LVTMTCX: DS90LV to +85°C SOIC M-LVDS, full duplex, type 1. DS90LVTM/TMTC. 1. 1. LVDS. or 5. to +85°C SOIC, TSSOP DS92LVATM. 1. SOIC M-LVDS, full duplex, type 2. DS91DTM. 1. 1. M-LVDS. MHz. . to +85°C. SOIC M-LVDS, full duplex, type 1. DS90LVTM/TMTC. 1.

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National has recently moved to 2-letter package code suf?

DS90LV datasheet & applicatoin notes – Datasheet Archive

Serializes 24 bits at 5 to 43 MHz to Mbps? National leverages its high performance analog signal conditioning expertise to provide solutions that extend cable reach, reduce jitter dd90lv048a transmit ultra-clean video signals that meet or exceed speci? DP reference design available DP reference design available interface. Zero volts on the receiver thresholds will always result in a logic LOW.


ds90lva, buy ds90lva, specification & datasheets

Fractional-N PLL programmable up to 4th order? National Semiconductor Corporation, September Up to 10 dB improvement over next best monolithic competitor? Also available 2 x 2 and tmt x 4 crosspoint switches as well as 1: Total maximum jitter 31 ps 1. Drives 10m twisted pair cable?

Single and dual channel integrated 2: Low phase noise VCO with integrated tank inductor and programmable output power level? Partially integrated adjustable loop? The application example below highlights the elegant dual differential interface between the LMH reclocker and LMH dual cable driver. Receiver automatically locks to any data pattern without external clock?

The diagram helps you to ds90lv048aa The chipset is fully AEC-Q quali? Channel Link SerDes n: Available in 12 x 12 mm TQFP packaging? Coax Length based on 0. A complete evaluation kit reference design is available. Very low phase noise and spurs?


Common mode extended to The DS90UR deserializer requires no external clock reference, reducing receiver board complexity and cost. Industrial Connectivity Made Easy. In addition to providing a failsafe, type 2 receivers can be used in Wired-Or logic. Type 2 receivers have a built-in failsafe where the receiver threshold is offset by mV.


Tight 50 mV receiver thresholds add to noise margin? Choice of second reclocked output or low-jitter, differential, data-rate clock output? All other brand or product names are trademarks or registered trademarks of their respective holders. DC-balance encoding for AC-coupled and optical interconnects? Tmct or de-emphasis pre-distorts the output signal to compensate for the?

Two differential, reclocked outputs? Integrated termination saves board area, improves signal quality? M-LVDS is optimized for multipoint including features critical to multipoint applications such as: LVDS crosspoints, muxes, and buffers? Low 34 mA typ power consumption?

Fast lock, cycle slip reduction with timeout counter? Cs90lv048a serializers, cable drivers, equalizers, reclockers, etc. F Coaxial Cable 1. This evaluation kit can be reworked to accept non MHz, nonbit devices if necessary.